+ C B A | Z + ========= + 0 0 0 | 1 + 0 0 1 | 1 + 0 1 0 | 1 + 0 1 1 | 1 + 1 0 0 | 1 + 1 0 1 | 0 + 1 1 0 | 0 + 1 1 1 | 0 +
Please add the appropriate pulldown network of mosfet + switches connected to node Z to implement the truth table above, with + \(R_{ON}\) of the mosfets chosen so that \(V_{ol}\) of the logic gate is less than + \(0.25V\) for any combination of inputs. In the schematic tool, the mosfet + model has \(V_{th} = 0.5V\), so \(V_{ol} \lt 0.25V\) + will ensure that when the output of the logic gate is 0, if it is used + as the input to some other logic gate, the mosfet to which + it connects will be off. + +
On page 305 of the text we + see from Equation (6) that \(R_{ON} = R_n \frac{L}{W}\). In the + schematic tool, the mosfet model has \(R_n \approx 26.5k\Omega\) when + using a \(3V\) power supply. To adjust \(R_{ON}\), double click the + mosfet and select an appropriate value for the W/L parameter. For + example, setting a mosfet's W/L to 10 would result in \(R_{ON} = + 2.65k\Omega\). + +
Note that the "Plot offset" property of the scope probes + on the A, B and C signals has been set so that the plots will not + overlap, making it easier to see what's happening. + +
Please do not change the voltages of the voltage sources or the + resistance of the pullup resistor. + +
Hint: you'll only need 3 mosfet switches to implement the gate. + +
When the gate is correctly implemented, the plot produced by the transient + analysis should like similar to the following figure. + +
+ Figure 1. Example plot output +
Food for thought: You'll notice there are little spikes, + sometimes called glitches, in the output waveform (see the + bottom cyan-colored waveform in Figure 1). These only occur when the + A and B inputs are changing simultaneously and the C input is high. + Can you explain why? Think about what is happening in the pulldown + circuitry at the time the glitches occur. + +